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Low Pin Count Test with Embedded Compression
Mentor Graphics
Description
This webcast discusses methodologies that enable designers to reduce the number of pins and top level routing required for the application of high quality test. Topics include: (1) High test compression with as few as 1 or 2 test channels, (2) Minimize congestion in top level routing using 1 or 2 test channels to access internal blocks, (3) Sample of real world LPCT implementations, and (4) Ways boundary scans achieve LPCT.
Company Overview
Mentor Graphics is a leader in electronic design automation. We enable companies to develop better electronic products faster and more cost-effectively. Our innovative products and solutions help engineers conquer design challenges in the increasingly complex worlds of board and chip design.
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